Within the HoLiSTEP project, the 388 nm holographic lithography test bench has reached two important technical milestones: 500 nm patterning and patterning on high topography wafers in photoresist, supported by verified aerial imaging and wafer exposure results.
The breakthrough results were achieved using Sub-Wavelength Holographic Lithography, a patterning approach designed as a cost-effective alternative to conventional projection photolithography. Unlike standard lithography methods that are primarily optimised for planar wafer surfaces, holographic lithography uses holographic masks to reconstruct the target image at the wafer plane. This enables tailored optical fields and creates the potential for both 2D and 3D high-resolution patterning in a single exposure.
The HoLiSTEP 388nm test-bench demonstration showed that holographically generated aerial images can be transferred into photoresist for 500 nm patterning on flat silicon wafers. It also demonstrated two-level image generation across surfaces separated by 100 µm at one exposure, highlighting the potential of holographic lithography for applications involving complex topographies such as stepped surfaces, sidewall slopes, or vertically separated device layers.
A further set of experimental results focused on single-exposure patterning in spray-coated resist on structured silicon wafers with 100 µm deep etched cavities. These wafers included regular cavity structures and were designed to assess the ability of holographic lithography to expose both the top wafer surface and the cavity bottom surface in one exposure. The results confirmed that structured wafers with deep cavities can be exposed in a single holographic exposure, with pattern quality on the top wafer surface and in the cavities showing comparable feature quality.
For industry, the significance of this result goes beyond the 500 nm feature size. Together, the milestones point to a patterning approach that combines sub-micron resolution with greater flexibility for structured, non-flat, and multi-level substrates; areas where conventional single-plane exposure methods become technically demanding or process-intensive. This capability is directly relevant to industrial sectors where substrate complexity is increasing. In MEMS, integrated photonics, advanced packaging, sensors, micro-optics, and heterogeneous integration, final pattern quality can be affected by resist coating uniformity, substrate height variation, surface roughness, and focus control. Holographic lithography offers a different route by enabling the exposure field to be designed for more complex surface geometries.
Holographic masks also offer potential manufacturing advantages. Their structures can be based on relatively simple elements, while image correction and resolution enhancement are embedded during the mask synthesis stage. This means that more complex image-generation requirements do not necessarily translate into proportionally more complex physical mask structures.
The next step for HoLiSTEP is to adapt the verified 388 nm test-bench capability toward the 345nm industrial platform, moving closer to the wavelength, resolution, and system architecture required for future industrial deployment. This transition is a critical stage in translating the current 500 nm validation result into a more advanced holographic stepper concept for sub-micron manufacturing applications.
Industry Engagement Opportunity
The HoLiSTEP project is entering an important phase for industry engagement and welcomes discussions with companies working in MEMS, photonics, advanced packaging, sensors, micro-optics, semiconductor equipment, materials, and high-value microfabrication who are well positioned to help define relevant use cases, process requirements, substrate formats, and performance targets for future industrial deployment.
Contact the HoLiSTEP project at HoliSTEP@Modus.ltd.
Keep up to date with the HoLiSTEP achievements on our LinkedIn (@Holistep-project)
